This invention relates generally to integrated circuits and more particularly to a novel method of fabricating a semiconductor device in an integrated circuit by capping a conductive layer with a nitride layer during salicidation.
In recent years the advancement of very large scale integration ("VLSI") technology has resulted in a need to fit more and more individual semiconductor devices such as transistors into smaller and smaller areas of an integrated circuit chip. The dimensions of these devices have reached the submicron range, and it has become increasingly difficult to make adequate electrical contacts for interconnecting such devices.
A relatively recent development in the art of fabricating semiconductors has been the self-aligning silicide process ("salicidation"). During this process successive layers of a conductive material and silicon are deposited over a substrate and then are annealed at a high temperature, forming a conductive silicide layer which then can be utilized for the establishment of electrical contacts with the various regions of the device. This process offers numerous advantages including reduced parasitic resistance in gate, diffusion and interconnect areas of the device and improved circuit packing density.
Titanium is nearly always used as the conductive material because the annealing of titanium and silicon yields titanium silicide (TiSi.sub.2) which is characterized by relatively low resistivity and good thermal stability and because of the ability of titanium to dissolve silicon native oxide during annealing to form silicide more consistently than other conductive materials.
Successful formation of titanium silicide is dependent on an absence of impurities between the titanium and the silicon. Any thin oxide or polymer residue left over from a previous step can prevent silicide formation. In addition, titanium reacts readily with any traces of oxygen that may be present. Oxygen contamination in the furnace must be less than about three parts per million ("PPM") in order to prevent such a titanium-oxygen reaction and permit the formation of titanium silicide to proceed reliably. This requires a leakproof system and a high rate of flow of very pure nitrogen gas during wafer loading and annealing, requirements which make the process costly to carry out and difficult to repeat.
Moreover, to successfully accomplish salicidation in a device having dimensions in the submicron range requires the solution of several other problems, among them minimizing drain-to-gate, source-to-gate, and junction leakage, preserving gate oxide integrity, and avoiding any adverse effects of dopant restribution or discontinuity of long polycides.
As a result of all these limitations, the depositing of the titanium and the subsequent high-temperature annealing are extremely difficult to control.
It has been proposed (Tang, T., C. C. Wei, R. Haken, H. Kawasaki, and R. Chapman in Symposium on VLSI Technology 1988, page 69) to add a sacrificial dielectric cap layer after depositing the titanium and strip back after sintering. However, the etch back process which must be performed as part of this technique has created many device and process complexities.
From the foregoing it will be apparent that there remains a need for a practical way to obtain the benefits of salicidation during fabrication of a semiconductor device.